全部技能

Generate synthesizable RTL source files from the architecture plan and spec extraction results. Use when the user needs to turn an RTL architecture plan into actual SystemVerilog module files with ports, registers, FSM skeletons, and datapath structure.

Plan RTL framework, module partitioning, implementation priorities, and scaffold responsibilities from reviewed front-end design facts. Use when the user needs to move from reviewed spec intent into an implementation-ready RTL architecture.

Plan top-level RTL integration, testbench bring-up, filelist structure, and Makefile organization for a digital front-end project. Use when the user needs to move from module planning into coherent top integration and practical compile or simulation preparation.

Three modes — (1) Generate synthesizable Verilog RTL from architecture spec when no RTL exists yet. (2) Review integration contracts and filelist of existing RTL. (3) Apply targeted RTL fixes from verification triage diagnostics. Do NOT use for compilation, simulation, testbench generation, SDC constraints, or lint/CDC checks.

Plans RTL hierarchy, defines module interfaces, guides synthesizable SystemVerilog coding, runs lint/CDC quality checks, and prepares RTL handoff for verification and synthesis. Supports open-source lint flows with Verilator and Slang, plus commercial EDA checks when available.

Evaluates architecture candidates from product requirements, models performance and PPA, compares tradeoffs, and prepares a microarchitecture handoff package for RTL. Supports open-source modelling with Python, gem5, McPAT and CACTI, with optional commercial EDA alternatives.