Chip Architecture Evaluation（Opensource Digital IC design）

Name: Chip Architecture Evaluation（Opensource Digital IC design）
Author: 中科麒芯

RTL设计与集成

中科麒芯·v1.0.0最新版

Evaluates architecture candidates from product requirements, models performance and PPA, compares tradeoffs, and prepares a microarchitecture handoff package for RTL. Supports open-source modelling with Python, gem5, McPAT and CACTI, with optional commercial EDA alternatives.

InterfaceOpensource Digital IC designQoRRTL-DesignRTL-IntegrationPolyForm-Noncommercial-1.0.0

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name:chip-design-architecture

description:Use when evaluating chip architecture candidates, decomposing a product spec into hardware requirements, modeling performance, estimating power/area, assessing technical risk, or preparing a microarchitecture handoff package for RTL. Trigger even when the user only asks for architecture tradeoffs, PPA estimation, gem5 modelling, McPAT area estimates, risk review, or a spec-to-microarchitecture workflow.

license:PolyForm-Noncommercial-1.0.0

metadata:

author:中科麒芯

organization:中科麒芯智能技术（南京）有限公司

homepage:https://www.ickylin.com/

contact:info@ickylin.com

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