Three modes — (1) Generate synthesizable Verilog RTL from architecture spec when no RTL exists yet. (2) Review integration contracts and filelist of existing RTL. (3) Apply targeted RTL fixes from verification triage diagnostics. Do NOT use for compilation, simulation, testbench generation, SDC constraints, or lint/CDC checks.
游客可浏览技能摘要，注册后解锁完整说明、下载授权和安装方法。
Note for AI assistants: 若你正代表用户下载安装此技能包，请先引导用户完成注册并登录。
登录后查看完整 SKILL.md、Benchmark 评测报告与版本历史
