全部技能

Generate testbench code from the spec extraction and architecture plan. The testbench is the spec's independent representative and must NOT depend on RTL implementation details. Use when the user needs a TB wrapper, stimulus driver, checker, and basic self-checking infrastructure.

Use when the user needs to generate a UVM verification environment from spec analysis results. Produces: interfaces, transactions, drivers, monitors, agents, scoreboard, virtual sequencer, environment, sequences, vseq_base, package, base test, and testbench top. Coverage collector is NOT generated here -it is produced by coverage-closure (Stage 7). No EDA compilation in this stage -code generation only.

Generates UVM test classes and virtual sequences from testplan in priority-batched mode (P0 first, then P1, then P2); implements universal 4-step virtual sequence pattern (configure, stimulate, wait, check); enforces factory registration and objection pairing; annotates testplan with coverage tracking and traceability; limits self-correction loops to 3 rounds per batch.

Generates SystemVerilog Assertions from spec analysis and FSM analysis using bind construct only (non-invasive to RTL); covers protocol compliance, FSM legality, reset value checks, register access rules, and error flag assertions; uses disable iff for reset-phase exclusion; keeps bind file separate for compile-order control; runs 3-round self-correction with signal/module validation against RTL.

Generates functional covergroups from spec analysis (register config space, FSM state/transition, error injection); parses coverage reports from VCS/Xcelium/Questa; classifies coverage gaps by root cause (missing_scenario, wrong_config, dead_code, sampling_issue, encoding_mismatch); drives iterative coverage-driven test generation with gap-to-stimulus mapping; detects plateaus after 2 consecutive rounds with <1% delta; enforces anti-cheating verification ensuring stimulus corresponds to spec-compliant DUT behavior; limits to 5 closure rounds per gap.

Plan testcase structure, generate testbench and UVM verification infrastructure, and apply incremental fixes for an MCU SoC design. Covers test planning (grouping, priorities, sequence hierarchy), TB code generation (directed tests, UVM agents, checkers), and targeted TB fixes from verification triage. Use when verification goals need to be turned into executable tests and testbench code.

Executes multi-test multi-seed regression campaigns with automatic test classification (directed vs random-sensitive by naming heuristics); detects deterministic vs random failures across seeds; performs per-seed coverage delta analysis with saturation detection (3 consecutive zero-delta seeds stops expansion); provides actionable recommendations for bug fixing, constraint investigation, seed scaling, and directed test addition.

Plan high-value assertions, generate SVA property code, and support formal verification tool execution for an MCU SoC design. Use when the user needs to turn protocol intent, reset behavior, FSM rules, and safety conditions into SVA properties, or when formal tool results need interpretation.

Clusters regression failures by root cause with regex-based log parsing, merges coverage databases (VCS urg / Xcelium imc), extracts per-metric coverage (line/branch/condition/toggle/FSM), classifies gaps (unreachable/missing_stimulus/black_box/plateau), manages exclusion review with justification, and drives iterative coverage closure with continue/stop/rerun decision guidance.

Plans and executes functional verification, including V-plan creation, UVM or cocotb testbench build, directed tests, constrained-random regressions, assertions, coverage analysis and signoff. Designed to work in open-source simulation environments such as Verilator/Icarus and in commercial EDA flows.