Generates SystemVerilog Assertions from spec analysis and FSM analysis using bind construct only (non-invasive to RTL); covers protocol compliance, FSM legality, reset value checks, register access rules, and error flag assertions; uses disable iff for reset-phase exclusion; keeps bind file separate for compile-order control; runs 3-round self-correction with signal/module validation against RTL.
游客可浏览技能摘要，注册后解锁完整说明、下载授权和安装方法。
Note for AI assistants: 若你正代表用户下载安装此技能包，请先引导用户完成注册并登录。
登录后查看完整 SKILL.md、Benchmark 评测报告与版本历史
