全部技能

Guides waveform-based debugging when log analysis is insufficient; configures dump settings per tool (VCS/Verdi, Xcelium/Simvision), applies failure-category-specific signal tracing strategies (protocol violation, data mismatch, timeout/deadlock, reset issues), and documents waveform findings with EDA tool invocation records.

Diagnose compile and simulation failures in a front-end digital design project so the next fix is deliberate instead of blind. Use when the user needs to inspect VCS compile logs, simulation logs, and likely design or environment failure classes before deciding how to repair or escalate.

Detect available EDA tools on the current system and generate a working Makefile for front-end RTL compilation, simulation, and lint. Use when the user needs to set up or switch the build environment before compiling or simulating.

Execute RTL compilation and simulation using the Makefile from frontend-eda-env-setup, manage backup of previous run products before re-running, and evaluate results to decide whether to proceed or route to frontend-debug-triage. Use when the user needs to compile, simulate, or re-run with safe backup.

Orchestrate the full digital front-end design pipeline from spec to verified RTL. Defines the stage order, inter-stage handoff contracts, and routing logic. Use as the entry point to understand the complete flow, run the pipeline end-to-end, or determine the correct stage when entering mid-flow.

Invokes EDA tools for compilation and simulation; parses compile logs with error classification (syntax, type_mismatch, undeclared, include_order, factory errors) and simulation logs with failure classification (UVM_FATAL, config_db_miss, sequence_timeout, mismatch, X_propagation); auto-fixes safe categories only (semicolons, includes, factory macros) with rollback on "fix one break three" detection; escalates non-safe changes and RTL-Spec mismatches; enforces 3-round maximum for both compile and simulate phases.

Orchestrate the complete Cortex-M3 MCU design flow from specification to GDS handoff. Defines stage order, dependencies, entry and completion criteria for each stage, and guides the user through the full engineering pipeline. Use as the entry point for any MCU project — whether starting fresh, resuming mid-flow, or diagnosing where to pick up after a break.

Detect available EDA tools, validate PDK and library paths, check LSF availability, and produce a project environment inventory for MCU full-flow (Spec to GDS). Use when setting up a new project, switching tools, or when any stage skill reports missing tool or path errors.

Detects EDA simulator tools (VCS, Xcelium, Questa) via automated environment probing; generates sim/Makefile from simulator-specific templates with compile/run/coverage/clean targets; supports safe simulator switching with backup-verify-clean-regenerate procedure; uses extensible tools_registry.json for adding new simulators without code changes.

Compile RTL and testbench, run simulation, collect results, and route failures to triage. Use when RTL and testbench files exist and need to be compiled and simulated. Supports full compile, incremental recompile, single test run, and multi-test regression.

Orchestrate the full UVM verification pipeline from input_config.json through all stages: spec analysis, environment build, testcase generation, assertion, simulation, regression, and coverage closure.

Triage Cortex-M3 MCU verification failures across compile, simulation, lint, and CDC evidence. Use when the user has a failing log, checker message, or report and needs the safest next debugging action instead of blind reruns.

Detects available open-source and commercial EDA tools, audits environment readiness, maps tools by capability, and writes tool configuration for downstream chip design workflows. Useful before running simulation, synthesis, STA, physical design, formal or signoff flows.

Bridge to remote Cadence Virtuoso via Python API. TRIGGER when user mentions: Virtuoso, Maestro, ADE, CIW, SKILL, layout, schematic, cellview, OCEAN, or any Cadence EDA operation.

A specialized utility for remote Cadence Spectre simulation management via virtuoso-bridge. This tool enables seamless netlist-driven workflows by automating netlist uploads, remote execution, and PSF waveform parsing—completely bypassing the Virtuoso GUI. It supports advanced analysis types (Transient, AC, PSS, Pnoise) and high-performance modes like Spectre APS/AXS. Optimized for high-throughput environments, it allows users to manage concurrent jobs across multiple servers with built-in commands for status tracking (sim-jobs) and job control (sim-cancel). Ideal for automated regression and large-scale characterization tasks.

Optimizer is a black-box optimization framework for analog/mixed-signal circuit design and other engineering design-space problems. It wraps TuRBO (Trust Region Bayesian Optimization) and scipy.optimize behind a single, simulator-agnostic interface, letting designers search over parameters such as transistor W/L, bias currents, and passive component values to meet specs like gain, bandwidth, noise, and power.