全部技能

Run signoff checks (parasitic extraction, STA, power analysis, DRC, LVS) and review results for an MCU SoC design. Generates tool scripts from templates, executes StarRC/PrimeTime/Calibre (Cadence equivalents supported but templates not bundled), parses results, and assesses tapeout readiness. Use when a routed design with GDS exists and needs signoff verification.

Generate final project reports, milestone summaries, and deliverable inventories from MCU SoC engineering outputs. Use when the user needs to package stage results into doc/final_report.md for teammates, customers, or the next engineering phase.

Run formal equivalence verification (Formality/Conformal) between RTL and synthesis netlist, and review results. Use when a synthesis netlist exists and logical equivalence must be confirmed before PnR, or when equivalence failures need diagnosis.

Validates timing constraints, runs multi-corner STA, reviews timing exceptions, analyzes critical paths and provides ECO guidance for timing closure. Supports open-source OpenSTA/OpenROAD timing analysis and commercial PrimeTime/Tempus signoff flows.

Runs or guides formal property verification and logical equivalence checking between RTL, netlists and ECO versions. Supports open-source SymbiYosys/Yosys flows first, while also covering Formality, Conformal, JasperGold and VC Formal when commercial EDA tools are available.