全部技能

Executes MMMC view setup, floorplanning with macro placement, placement, clock tree synthesis, routing, filler/tap/endcap cell insertion, and GDS export; parses post-route timing/area/power/congestion/DRC reports; identifies implementation hotspots (macro choke points, clock skew pressure, control fanout); applies retry-vs-rollback logic based on WNS severity and congestion overflow.

Plans and reviews the physical design flow from PDK analysis, floorplan, placement, CTS and routing through timing, power, area optimization and GDS signoff. Supports open-source OpenROAD/KLayout flows as well as commercial Innovus, ICC2 and Calibre-based EDA flows.