全部技能

Generates SDC timing constraints from spec clock definitions, produces synthesis scripts (DC/Genus), executes logic synthesis, analyzes QoR (WNS/area/power/cell count), validates constraint quality, evaluates clock gating effectiveness, and applies retry-vs-rollback decision rules based on timing slack and power budget thresholds.

Prepares synthesis constraints, explores compile strategies, generates gate-level netlists, checks timing/area/power QoR, performs netlist QC and prepares synthesis handoff. Supports open-source Yosys flows with Liberty libraries and commercial DC/Fusion/Genus flows.